In differential signaling it is conventional to convert from a low-common mode voltage domain to a high-common mode voltage domain. For example, a receiver may use a differential pair of NMOS transistors that require a relatively-high common mode voltage. But the transmitter, or other component of the system, may be using a low-common mode voltage.
For instance, in some high-speed wireline applications, receiver input signals are terminated at a low common mode voltage level, such as 0V or hundreds of mV. To further process the high-speed signal (e.g., 6-10 Gb/s), NMOS differential pairs are generally preferred over PMOS due to lower parasitics, though some applications use PMOS. A conversion buffer is used to convert the low common mode voltage high-speed signal to a high common mode voltage level.
To perform the level shifting to the high-common mode domain it is conventional to receive each differential input signal through a shunt capacitor. For example, one differential input signal may be denoted as rxinp (receiver input positive) whereas the complementary differential input signal may be denoted as rxinn (receiver input negative). Rxinp would be received through a shunt capacitor. Similarly, rxinn would also be received through a shunt capacitor. The shunt capacitors block the received common mode voltage such that the received signals are then boosted using, e.g., a voltage divider to provide the desired relatively-high common mode voltage. But such an arrangement generally only works for relatively high frequency differential signals. As the input frequency is reduced, the shunt capacitors would not only block the received common mode voltage but also the Alternating Current (AC) portion of the signal as well. Such a conventional level shifting arrangement is thus not suitable for some wideband applications.
There is thus a need in the art for improved common mode level shifters that work in both the low and high frequency domains (wideband operation).